This application claims the benefit of European Application No. 00400283.8, filed Feb. 10, 2000.
1. Technical Field
The present invention generally relates to optoelectronic/photonic devices and, more particularly, to a method and apparatus for passively aligning, tacking, and bonding an optoelectronic/photonic device with a matching substrate.
2. Discussion
Photonic component hybridization concerns integrating optical components on a substrate with optoelectronic/photonic devices. This technology involves electrically and mechanically bonding the optoelectronic/photonic device with the optical components (e.g. wave guides, gratings, etc.) on the substrate. A fundamental issue in photonic component hybridization is the accurate positioning of the device relative to the substrate. Attempts to ensure such positioning accuracy include active and passive alignment techniques.
A widely used passive alignment technique involves the use of flip-chip solder bonding. U.S. Pat. No. 5,499,312 discloses a method for passive alignment and packaging of optoelectronic components to optical wave guides using flip-chip bonding technology. This method completely relies on the solder surface tension and the design of the wettable pads to align the wave guides to the optoelectronic components. In this bonding sequence, a chip (e.g., the device) with a plurality of solder bumps formed thereon is roughly aligned over a substrate using a pick and place machine, the temperature of the assembly is then raised above the solder melting temperature, and, upon the solder melting, surface tension appears at all interfaces which moves the chip to the lowest potential energy point which corresponds to alignment with the substrate. Once the chip is aligned, the solder is cooled.
Tests have shown that such passive alignment techniques range in accuracy from a submicron level to more than 10 microns due to variations in the solder bonding process. Current accuracy requirements for photonic component hybridization is about 0.5 micrometers in the X, Y, and Z directions. As such, the uncertainty in alignment accuracy of this technique makes it unsuitable for photonic assemblies.
To eliminate the dependency of alignment accuracy on the solder bonding process, several techniques employing stops and standoffs have been employed. For example, German Patent No. 19 644 758 A1 discloses a technique wherein the chip to be attached has projections that are inserted into recesses on the substrate in a precisely fitted fashion. The dimensional accuracy of the projections and the recesses is determined either by lithography or by micro-milling or micro-drilling tolerances, typically less than one micrometer.
Another exemplary passive alignment technique is disclosed in U.S. Pat. No. 5,077,878. In this technique, two front pedestals and one side pedestal are provided on the surface of one chip and a vertical side wall is provided on the other chip. When mounted, the front face of the second chip contacts the two front pedestals of the first chip and the side wall of the second chip mates with the side pedestal of the first chip. This theoretically precisely aligns the two chips.
While tests have shown that some very good results can be obtained with the above techniques, results still depend upon the frictional forces between the stops on one chip and the edges or recesses in the other chip. This is a severe drawback for mass production. To overcome this drawback, some manufacturers have employed active alignment techniques.
One type of active alignment technique uses a flip-chip machine which yields very precise and accurate placement. Active alignment using commercially available flip-chip machines demonstrate accuracy tolerances of about 0.5 micrometers. However, such flip-chip machines are very expensive. As such, this active alignment technique is not cost-effective. In addition to the machine price, using such a machine does not allow multiple chip bonding. This results in a very slow production rate. Manufacturing process using such a machine are not only expensive but also very slow.
In view of the foregoing, it would be desirable to provide a method and apparatus for aligning and bonding a chip to a substrate which overcomes the drawbacks of the prior art.
The above and other objects are obtained by providing a first chip with a plurality of solder bumps and a plurality of recesses at preselected locations relative to the plurality of solder bumps. A second chip is provided with a plurality of solder pads and a plurality of projections at preselected locations relative to the plurality of solder pads. A plurality of solder bonds are coupled between at least one of the plurality of solder bumps and the plurality of solder pads, and the plurality of projections and the plurality of recesses. At least one of the plurality of recesses and the plurality of projections includes angled walls for capturing and directing the other of the plurality of recesses and the plurality of projections during reflow of the solder bonds such that the first chip aligns relative to the second chip under the surface tension of the solder bonds. According to another aspect of the present invention, vibrating waves are applied to the first and second chips during reflow to assist movement of the plurality of projections relative to the plurality of recesses.